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SY58627L
DC-to-6.4Gbps Backplane Receive Buffer with Four Stage Programmable Equalization and DC-Offset Control Preliminary
General Description
The SY58627L high-speed, low jitter receive buffer is optimized for backplane and transmission line data-path management applications. The SY58627L is capable of receiving serial data up to 6.4Gbps across up to 36 inches of FR4. The SY58627L differential input includes Micrel's unique, 3-pin input termination architecture that directly interfaces to any differential signal as small as 100mVpk (AC- or DC-coupled) without any termination resistor networks in the signal path. The outputs are 50 source-terminated CML optimized to drive 400mVpk into 50 (100 load across the output pair). The I/O termination is connected to a dedicated VTT pin for added bias flexibility. The SY58627L receiver input provides four levels of equalization to compensate for degraded signals resulting from transmission losses. The equalization is programmed with a three-bit interface. The SY58627L operates at 3.3V 10% supply and is guaranteed over the full industrial temperature range of -40C to +85C. The SY58627L is part of Micrel's high(R) speed, Precision Edge product line. All data sheets and support documentation can be found on Micrel's web site at: www.micrel.com.
Precision Edge(R)
Features
* Selectable equalizing network to optimize incoming data eye pattern * Four selectable equalization levels * Receives up to 36" FR4 PCB trace, or longer combinations of FR4+cable+interconnect * DC through 6.4Gbps data rate throughput * Integrated loopback capability * Unique, flexible I/O: - Patented, Internal termination to VTTIN pin interfaces to any differential AC- or DC-coupled signals - 50 source-terminated CML outputs minimize round-trip reflections - Wide input voltage range: 100mV to 1.3VPK - Output disable - DC-offset control with VTT I/O * Input Loss-of-Signal - Hysteresis included * 3.3V 10% supply voltage * -40C to +85C temperature range * Available in 32-pin (5mm x 5mm) MLFTM package
Applications
* * * * * ATE, T&M backplane management Serial backplane management Combination FR4+cable+interconnect receiver Fibre Channel, GigE, SONET/SDH data transmission Electrical interface and interconnect applications that require DC-offset control
Precison Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
January 2006
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SY58627L
Functional Block Diagram
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SY58627L
Ordering Information(1)
Part Number SY58627LMG SY58627LMGTR(2)
Notes: 1. 2. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. Tape and Reel.
Package Type MLF-32 MLF-32
Operating Range Industrial Industrial
Package Marking SY58627L with Pb-Free bar-line indicator SY58627L with Pb-Free bar-line indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
32-Pin MLF
TM
(MLF-32)
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SY58627L
Pin Description
Pin Number Pin Name Pin Function Differential receiver input pair: This input pair is the differential signal input to the device. It accepts AC- or DC-coupled signals as small as 100mV (200mVPP). The loss-of-signal (LOS Level) includes a small amount of hysteresis to prevent the lossof-signal output from oscillating when no signal is present. RXIN and /RXIN internally terminate to the VTTIN pin through 50. Please refer to the "Input Interface Applications" section for more details. RXIN, /RXIN differential inputs recommended be 90mVPK to ensure valid outputs. Consider disabling the outputs when the differential input is not present, or < 90mVPK (e.g.: Hot Swap Applications). Input termination center-tap: RXIN and /RXIN terminate to VTTIN. The VTTIN pin provides a center-tap to the internal termination network for maximum interface flexibility, and DC-offset capability. Please refer to the "Input Interface Applications" section for more details. Reference voltage: This output biases to VCC-0.84V. It is used for AC-coupling the input pair (RXIN, /RXIN). Connect VREF-AC directly to the VTTIN pin. Bypass with 0.01F low ESR capacitor to VCC. Maximum sink/source current is 1.5mA. Due to the limited drive capability, the VREF-AC pin is only intended to drive the VTTIN pin. Leave VREF-AC pin floating when not used. Please refer to the "Input Interface Applications" section for more details. Input logic threshold control voltage for logic control threshold settings other than LVTTL/CMOS. This input control pin can be externally biased to set the proper threshold for all the logic control pins, /RXEN, LBSEL, 3-bit equalization control, and /RXLBEN. For standard LVTTL/CMOS control, simply leave the VTH pin floating and the threshold voltage defaults to VCC/2 (When VEE = 0V). For LVPECL thresholds, set VTH to VCC-1.3V. TTL/CMOS (or VTH controlled) compatible control input for the RXQ output pair. When pulled HIGH, the RXQ output pair is disabled. This input is internally connected to a 25k pull-down resistor and will default to a logic LOW state (Enable) if left open. When disabled, the RXQ output goes LOW, and /RXQ output goes HIGH. Default threshold is VCC/2 when VTH pin is floating. TTL/CMOS (or VTH controlled) compatible control input for RXLBQ output pair. When pulled HIGH, the RXLBQ output pair is disabled. This input is internally connected to a 25k pull-down resistor and will default to a logic LOW state (Enable) if left open. When disabled, the RXLBQ output goes LOW, and /RXLBQ output goes HIGH. Default threshold is VCC/2 when VTH pin is floating. In normal operating mode, when the RXLBQ output pair is not needed, disable the RXLBQ output pair (/RXLBEN = HIGH) to minimize noise. Loopback MUX select control: The TTL/CMOS (or VTH controlled) compatible input selects the input to the Loopback mode multiplexer. When LBSEL input is logic HIGH, Loopback mode is selected, and the TXLBIN input pair is selected to pass through the RXQ and RXLBQ output pairs. Note that the LBSEL pin is internally connected to a 25k pull-down resistor and will default to a logic LOW state if left open (normal operation). The Loopback MUX includes internal input isolation to minimize crosstalk. Loopback differential input pair: AC-coupled, CML-compatible input. This input pair includes internal termination connected to an internal VBB for an AC-coupled bias configuration. For local Loopback operation, the TXLBIN input pair receives a signal from the SY58626L transmitter TXLBQ output pair. The input signal from TXLBIN does not have any equalization. When the SY58627L Loopback mode is selected (LBSEL = HIGH), the signal at TXLBIN is directed to the RXQ and RXLBQ output pairs.
3, 4
RXIN, /RXIN
6
VTTIN
7
VREF-AC
27
VTH
23
/RXEN
15
/RXLBEN
10
LBSEL
11, 12
TXLBIN, /TXLBIN
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SY58627L
Pin Description (Continued)
Pin Number Pin Name Pin Function Receiver loopback CML compatible output pair. When the SY58627L is in local Loopback mode (LBSEL = 1), RXLBQ output is directed from TXLBIN (no equalization). When the SY58627L is in normal mode (LBSEL = LOW) and the RXLBQ output is not required, disable the RXLBQ output (/RXLBEN = HIGH) to minimize switching noise. This differential output pair is optimized to drive 400mVPK swing into a 50 load (100 across the pair). The RXLBQ output pair includes 50 internal source termination resistors. Receiver differential CML compatible output pair: This CML-compatible output pair is the equalized signal seen at the RXIN input pair and is optimized to drive 400mVPK swing into a 50 load (100 across the pair). The RXQ output pair includes 50 internal source termination resistors. When the SY58627L is in Loopback mode (LBSEL = HIGH), then the RXQ output signal is directed from the unequalized TXLBIN input. Please contact factory Applications Engineers. Output termination center-tap: Each side of the RXQ differential output pair terminates to the VTTOUT pin through 50. The VTTOUT pin provides a center-tap to the output termination network for maximum interface flexibility, and DC-offset capability. Please refer to the "CML Output Interface Applications" section for more details. TTL/CMOS (or VTH controlled) compatible, 3-bit control interface. There are four levels of equalization, as shown in the "Equalization Select Truth Table." When the MSB is logic HIGH, the RXQ output pair will not include any equalization. 28 29 30 EQ2( MSB) EQ1 EQ0 000 = lowest equalization setting 001 = medium equalization setting 010 = medium-high equalization setting 011 = highest equalization setting 1XX = equalization bypass 1, 8, 9, 16, 17, 24, 25 2, 5, 18, 22, 31, 32 VCC VEE, Exposed Pad Positive Power Supply: Connect to +3.3V power supply. Bypass with 0.1F//0.01F low ESR capacitors as close to VCC pins as possible. Ground: Ground pins and exposed pad must be connected to the same ground plane.
13, 14
RXLBQ, /RXLBQ
21, 19
RXQ, /RXQ
26
LOS
20
VTTOUT
Equalization Select Truth Table
Disable EQ (MSB = EQ2) 0 0 0 0 1 Equalization Select (EQ1) 0 0 1 1 X Equalization Select (EQ0) 0 1 0 1 X Typical FR4 Length 9" 18" 24" 36" NA Equalization Low Medium Low Medium High High Disabled
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SY58627L
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ...............................................-0.5V to +4.0V Input Voltage (VIN) ...................................................... -0.5V to VCC Input Current (RXIN, /RXIN, 120mins) ............................... 67mA CML Output Current (IOUT) Continuous (120mins)..................................................... 67mA Surge .............................................................................. 100mA Termination Current VT .................................................................................. 100mA VREF-AC Current Source/sink current on VREF-AC.......................................... 2mA Lead Temperature (soldering, 20 sec.) ..............................+260C Storage Temperature (TS) ..................................... -65C to 150C
Operating Ratings(2)
Supply Voltage (VCC) .................................... +3.0V to +3.6V Ambient Temperature (TA) ............................ -40C to +85C (3) Package Thermal Resistance TM MLF (JA) Still-Air ...............................................................34C/W MLFTM (JB) Junction-to-Board ..............................................20C/W
DC Electrical Characteristics(4)
TA = -40C to +85C; unless otherwise stated.
Symbol VCC IEE Parameter Power Supply Power Supply Current Max VCC, includes 50 internal source resistors, no external load current 45 90 Input signal swing applied to transmission line input up to 36 in. (driver side of RXIN) See Figure 4a. See Figure 4b. Condition Min 3.0 Typ 3.3 210 Max 3.6 260 Units V mA
RIN RDIFF_IN VIN_TRANS
Input Resistance (RXIN-to-VTTIN) Differential Input Resistance (RXIN-to-/RXIN) Transmission Line Input Voltage Swing (RXIN, /RXIN) Input Voltage Swing (RXIN, /RXIN) Differential Input Voltage Swing |RXIN-/RXIN| Input High Voltage (RXIN, /RXIN) Input LOW Voltage (RXIN, /RXIN) RXIN-to-VTTIN (RXIN, /RXIN) VTTIN Voltage Range VTTOUT Voltage Range Loss-of-Signal Input Levels Input Return Loss Voltage applied to VTTIN pin Voltage applied to VTTOUT pin LOS Assert LOS De-assert 100MHz to 3.5GHz
50 100
55 110

0.20 0.1 0.2 VEE+1.6 VEE+1.4 VCC VIH-0.1 1.5 VCC-1.5 VCC-0.4 Note 5 Note 5 10 VCC-0.95 VCC-0.84 VCC-0.7 VCC+1.5 VCC 1.3
VPK VPK VPP V V V V V mVPK dB V
VIN VDIFF_IN VIH VIL VTTIN VTTIN Range VTTOUT Range LOS
VREF-AC
Notes:
Output Reference Voltage
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
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SY58627L
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JA and JB values are determined for a 4-layer board in still air unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. TJ < 125C. 5. Please contact factory Applications Engineers.
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SY58627L
RXQ and RXLBQ Output DC Electrical Characteristics(6)
VCC = 3.3V 10%; VEE = 0V; TA = -40C to + 85C; RL = 100 across output pair; unless otherwise stated.
Symbol VOH VOUT Parameter RXQ & RXLBQ Output High Voltage Output Voltage Swing (RXQ, /RXQ) (RXLBQ, /RXLBQ) RXQ & RXLBQ Differential Output Voltage Swing |RXQ-/RXQ| |RXLBQ-/RXLBQ| Output Impedance Condition RL = 50 to Vcc See Figure 4a. 325 See Figure 4b. 650 45 800 50 55 mVPP 400 mVPK Min VCC-0.040 Typ VCC-0.010 Max VCC Units V
VDIFF_OUT ROUT
Logic Control DC Electrical Characteristics(6)
VCC = 3.3V 10%; VEE = 0V; TA = -40C to + 85C; unless otherwise stated.
Symbol VIH VIL IIH IIL VTH Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Threshold Input Voltage Voltage applied to pin (VEE = 0V) -300 1.4 VCC/2 2.6 Condition All control input pins All control input pins Min VTH+0.2 VEE Typ Max VCC VTH-0.2 300 Units V V A A V
TXLBIN Input DC Electrical Characteristics(6)
VCC = 3.3V 10%; VEE = 0V; TA = -40C to + 85C; RL = 100 across output pair; unless otherwise stated.
Symbol RDIFF_IN VIN VDIFF_IN
Notes: 6. The circuit is designed to meet the DC specifications, shown in the above table, after thermal equilibrium has been established. 500lfpm Airflow. TJ < 125C.
Parameter Differential Input Resistance (TXLBIN-to-/TXLBIN) Input Voltage Swing (TXLBIN, /TXLBIN) Differential Input Voltage Swing |TXLBIN-/TXLBIN|
Condition
Min 90
Typ 100
Max 110 1.3
Units VPK VPP
See Figure 4a. See Figure 4b.
0.1 0.2
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SY58627L
AC Electrical Characteristics(7)
VCC = 3.3V 10%; VEE = 0V; TA = -40C to + 85C; RL = 100 across output pair; unless otherwise stated.
Symbol Freq tpd tEN tLB_EN tLBSEL tPROG tpd Tempco tSKEW tJITTER tr, tf
Notes: 7. High-frequency AC-parameters are guaranteed by design and characterization. 8. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 9. Random jitter is measured with a K28.7 pattern at: 6.4Gbps. 10. Deterministic jitter is measured with both K28.5 and 2 -1 PRBS pattern, at 4.25Gbps/6.4Gbps. 11. Contact factory for updated random jitter and deterministic jitter limits.
23
Parameter Data Rate Throughput (RXQ & RXLBQ) Differential Propagation Delay RXQ Enable/Disable Time RXLBQ Enable/Disable Time Loopback Select Time Programming Logic Control Time Differential Propagation Delay Temperature Coefficient Part-to-Part Skew Random Jitter (RJ) Deterministic Jitter (DJ) Output Rise/Fall Time (20% to 80%)
Condition NRZ Data RXIN-to-RXQ, no equalization TXLBIN-to-RXQ /RXEN /RXLBEN LBSEL 3-bit equalization control update-to-valid RXQ
Min DC 150
Typ
Max 6.4
Units Gbps ps ps ps ps ps ns fs/oC
250 250 425 425 350 1 120
450 650 600
Note 8 Note 9 Note 10 At full output swing 20 50
200 Note 11 Note 11 80
ps psRMS psPP ps
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SY58627L Loopback The SY58627L features a loopback test mode, activated by setting LBSEL to logic HIGH. Using the SY58627L with the SY58626L enables local loopback and link side loopback, shown in Figures 2b and 2c. This mode enables an external loopback path, bypassing circuitry on both local and link side. Please refer to Table 1 and Figure 3 for Loopback Control information.
Detailed Description
The SY58627L is a high speed, low jitter receive buffer with integrated loopback capability. This buffer also provides input signal detect and output disable. Four selectable levels of equalization are included with the receiver. Equalization allows for faster data rates and longer distances by reducing the effects of intersymbol interference (ISI) caused by long cable and trace lengths. Input equalization supports data rates up to 6.4Gbps. DC-Offset Capability The SY58627L transmitter includes the VTTIN and VTTOUT pin for maximum interface flexibility and DCoffset capability for the input and output, respectively. This feature allows for interfacing with different logic families without the use of AC-coupling. The output buffer has internal 50 source terminated CML outputs for minimizing round-trip reflections. Transmitter Disable and Shutdown The SY58627L disable function is initiated by pulling /RXEN to logic HIGH. In disable mode, RXQ goes to a LOW state and /RXQ goes to a HIGH state. The threshold for /RXEN is set with the VTH pin. When the VTH pin is floating, the VTH levels are TTL/CMOScompatible with a threshold voltage at VCC/2 (VEE = 0V). For PECL compatible levels, apply a VCC-1.3V voltage at the VTH pin. Please refer to, "Typical Operating Characteristics" for more details.
Figure 2a. Normal Operation
Figure 2b. Local Loopback Mode
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SY58627L
LBSEL 0 Normal Mode 0 0 0 Link Side Loopback Mode 1 1 1 1
/RXLBEN 0 0 1 1 0 0 1 1
/RXEN 0 1 0 1 0 1 0 1
RXQ RXIN 0 RXIN 0 TXLBIN 0 TXLBIN 0
RXLBQ RXIN RXIN 0 0 TXLBIN TXLBIN 0 0
Table 1. Transmit Loopback Control Signal
Figure 2c. Link Side Loopback Mode
Figure 3. Loopback Control
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SY58627L
Typical Operating Characteristics
VCC = 3.3V 10%; VIN > 400mV; TA = 25C, RL = 100 across output pair; unless otherwise stated.
8in FR4 Output without SY58627L 23 (4.25Gbps PRBS 2 ) 8in FR4 Output with SY58627L 23 (4.25Gbps PRBS 2 )
Output Swing (100mV/div.)
Output Swing (100mV/div.)
Time (50ps/div.) 8in FR4 Output without SY58627L 23 (6.4Gbps PRBS 2 )
Time (50ps/div.) 8in FR4 Output with SY58627L 23 (6.4Gbps PRBS 2 )
Output Swing (100mV/div.)
Time (50ps/div.)
Output Swing (100mV/div.)
Time (20ps/div.)
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SY58627L
Typical Operating Characteristics (Continued)
VCC = 3.3V 10%; VIN > 400mV; TA = 25C, RL = 100 across output pair; unless otherwise stated.
1m FR4 Output without SY58627L (2.5Gbps PRBS 223) 1m FR4 Output with SY58627L (2.5Gbps PRBS 223)
Output Swing (100mV/div.)
Time (100ps/div.)
Output Swing (100mV/div.)
Time (100ps/div.)
1m FR4 Output without SY58627L (4.25Gbps PRBS 223)
1m FR4 Output with SY58627L (4.25Gbps PRBS 223)
Output Swing (100mV/div.)
Output Swing (100mV/div.)
Time (100ps/div.)
Time (50ps/div.)
1m FR4 Output without SY58627L (6.4Gbps PRBS 223)
1m FR4 Output with SY58627L (6.4Gbps PRBS 223)
Output Swing (100mV/div.)
Output Swing (100mV/div.)
Time (100ps/div.)
Time (25ps/div.)
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SY58627L
Typical Operating Characteristics (Continued)
VCC = 3.3V 10%; VIN > 400mV; TA = 25C, RL = 100 across output pair; unless otherwise stated.
5m Cable(1) Output without SY58627L 23 (4.25Gbps PRBS 2 ) 5m Cable(1) Output with SY58627L (4.25Gbps PRBS 223)
Output Swing (100mV/div.)
Time (50ps/div.)
Output Swing (100mV/div.)
Time (50ps/div.)
5m Cable(1) Output without SY58627L (6.4Gbps PRBS 223)
5m Cable(1) Output with SY58627L (6.4Gbps PRBS 223)
Output Swing (100mV/div.)
Time (20ps/div.)
Output Swing (100mV/div.)
Time (20ps/div.)
Output Disable
/RXQ HIGH RXQ LOW HIGH /RXEN LOW
Time (250ns/div.) Note: 1. Measurements made with 26AWG Amphenol Skew Clear Eye Opener Plus cable.
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SY58627L
Single-Ended and Differential Swings
Figure 4a. Single-Ended Voltage Swing
Figure 4b. Differential Voltage Swing
Input and Output Stages
Figure 5a. Simplified RXIN Differential Input Stage
Figure 5b. Simplified RXQ Differential Output Stage
Figure 5c. Simplified TXLBIN Differential Input Stage
Figure 5d. Simplified RXLBQ Differential Output Stage
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SY58627L
Input Interface Applications
option: may connect VTTIN to VCC Figure 6a. LVPECL Interface (DC-Coupled) Figure 6b. LVPECL Interface (AC-Coupled) Figure 6c. CML Interface (DC-Coupled)
Figure 6d. CML Interface (AC-Coupled)
Figure 6e. LVDS Interface (DC-Coupled)
Figure 6f. TXLBIN Interface (AC-Coupled)
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SY58627L
RXQ Output Interface Applications
Figure 7a. CML DC-Coupled Termination
Figure 7b. CML DC-Coupled Termination
Figure 7c. CML AC-Coupled Termination
RXLBQ Output Interface Applications
Figure 7d. CML DC-Coupled Termination
Figure 7e. CML DC-Coupled Termination
Figure 7f. CML AC-Coupled Termination
Related Product and Support Information
Part Number SY58626L Function DC-to-6.4Gbps Backplane Transmit Buffer with Selectable Output Pre-emphasis, I/O DC-Offset Control, and 200mV-3VPP Output Swing MLFTM Application Note HBW Solutions New Products and Applications Data Sheet Link www.micrel.com/product-info/products/sy58626l.shtml
www.amkor.com/products/notes_papers/MLFAppNote.pdf www.micrel.com/product-info/products/solutions.shtml
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SY58627L
Package Information
32-Pin MLFTM (MLF-32)
Package Notes: 1. 2. Package meets Level 2 Moisture Sensitivity Classification. All parts are dry-packed before shipment. Exposed pad must be soldered to a ground for proper thermal management.
3.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated.
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